Computer circuit memory systems are designed for a variety of purposes and have different characteristics. For example, main memory is usually implemented by dynamic random access memory (DRAM) chips and the DRAM system can have a data width that is selected according to its purpose. Modern DRAM memory is commonly implemented using double-data-rate (DDR) DRAM that provides efficient accesses using bursts. A central processing unit (CPU) having a cache with a 64-byte cache line size may fill or write back cache lines using eight DDR chips each organized with a by-eight (×8) data width. Since the memory system has a 64-bit data width, the CPU can access a complete 64-byte cache line using a burst length of eight. On the other hand, a graphics processing unit (GPU) having a cache with a 32-byte cache line size may fill or write back cache lines using four ×8 DDR memory chips to obtain a 32-bit width so that the GPU can access a complete 32-byte cache line using a burst length of eight. The caches themselves may also need dedicated memory to store tags and data. The cache memory system is typically implemented using static random access memory (SRAM). SRAM also can have various sizes and data widths for different caches. Thus a memory system that works well with a CPU may not work well with a GPU and vice versa, and it has been difficult to design memory systems capable of working for these various purposes.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well. Additionally, the terms remap and migrate, and variations thereof, are utilized interchangeably as a descriptive term for relocating.